This is a divisional application of U.S. application Ser. No. 10/722,461, filed Nov. 28, 2003, and now U.S. Pat. No. 7,110,283, the entire disclosure of which is hereby incorporated by reference.
The present invention relates to a semiconductor memory device and to a technology that is effective when applied to a semiconductor memory in which static memory cells are arranged.
In a semiconductor memory device of the type used, for example, in a semiconductor integrated circuit, a latch circuit for storing and retaining data comprises n channel type MOS transistors and their load elements. A signal input/output terminal of the latch circuit and its corresponding bit line are connected via an access transistor. The access transistor is normally configured as an n channel type MOS transistor. However, when an n channel type MOS transistor is used as the access transistor, the cell current at the time of a read operation becomes small according to the threshold voltage of the n channel type MOS transistor, its operating speed becomes slow and the speed of writing of data on the high level side becomes slow. Therefore, it has been proposed to use a semiconductor memory device wherein access transistors are configured as p channel MOS transistors (e.g., see the below-listed Patent Documents 1 and 2). In a circuit provided with p channel MOS transistors serving as access transistors, the potential of a storage node, which is stepped or pulled down by the corresponding access transistor, extends to a potential higher than ground potential (power supply VSS on the low potential side) by the threshold voltage of the access transistor. When this potential is higher than the reverse threshold voltage of a latch circuit, the writing of data (or its rewriting) cannot be performed. Therefore, there is a known technique wherein a terminal different from the terminal used for supply of a normal power supply potential GND on the low potential side is provided, and a potential higher by a predetermined level than the select level of a word line is supplied to that terminal to thereby make it possible to detect low level data of each bit line by means of a latch circuit, even if the potential of a storage node is reduced by the threshold voltage of the access transistor during a write operation, whereby the writing and rewriting of data can be reliably performed.
[Patent Document 1]                Japanese Unexamined Patent Publication No. Hei 9(1997)-231765        
[Patent Document 2]                Japanese Unexamined Patent Publication No. Hei 4(1992)-168694        